1. Field of the Invention
The present invention relates to a method and apparatus for driving a capacitive element such as a piezoelectric element or a liquid crystal element, etc.
2. Description of the Related Art
An apparatus for driving a capacitive element is known from, for example, Japanese Patent Application KOKAI Publication No. 59-224356. This apparatus will be described with reference to FIG. 13. As shown in FIG. 13, DC power supply V1 is connected to a series circuit of PNP transistor 1, variable resistor 5 and NPN transistor 2. DC power supply V2 is connected to a series circuit of PNP transistor 3, variable resistor 6 and NPN transistor 4. A piezoelectric element 7 as a capacitive element is connected between the collectors of the transistors 2 and 4. The piezoelectric element 7 surrounds the outer wall of the pressure chamber of a jet head. A timing pulse (/b) obtained by inverting the waveform shown in (b) of FIG. 14 is input to the bases of the transistors 1 and 2. A timing pulse (/a) obtained by inverting the waveform shown in (a) of FIG. 14 is input to the bases of the transistors 3 and 4.
When the transistors 1 and 4 are in the OFF state and the transistors 2 and 3 are in the ON state at time point t1, the positive electrode 8 of the piezoelectric element 7 is grounded, whereby positive driving voltage V2 is applied to the negative electrode 9 of the element 7 via the variable resistor 6. Since thus, a voltage is applied to the piezoelectric element 7 in a direction opposite to the polarization direction of the element 7, the element 7 is expanded and hence the volume of an ink chamber is increased. When the transistors 2 and 3 are turned off and the transistors 1 and 4 are turned on at time point t2, which is time period T1 later than the time point t1, the negative electrode 9 of the piezoelectric element 7 is grounded, and positive driving voltage V1 is applied to the positive electrode 8 via the variable resistor 5. Since thus, a voltage is applied to the piezoelectric element 7 in the same direction as the polarization direction of the element 7, the element 7 is contracted and hence the volume of the ink chamber is reduced, thereby discharging a recording liquid drip, i.e. ink, from the jet head.
When, at time point t3, which is time period T2 later than the time point t2, the transistor 1 is turned off, the transistor 3 is kept in the OFF state, the transistor 2 is turned on, and the transistor 4 is kept in the ON state, both the electrodes 8 and 9 of the piezoelectric element 7 are grounded, and therefore, the element 7 is returned to its initial state.
If this driving apparatus is configured using MOS transistors, a configuration as shown in FIG. 15 is obtained. Specifically, a series circuit of PMOS transistor 11 and NMOS transistor 12, and a series circuit of PMOS transistor 13 and NMOS transistor 14 are connected between a driving voltage VAA and the ground. A signal from logic circuit 15 is supplied to the gate of the PMOS transistor 11 via level shifter (L/S) 16 and pre-buffer 17. The signal from logic circuit 15 is also supplied to the gate of the NMOS transistor 12 via level shifter (L/S) 18 and the pre-buffer 17. Further, a signal from logic circuit 19 is supplied to the gate of the PMOS transistor 13 via level shifter (L/S) 20 and pre-buffer 21. The signal from logic circuit 19 is also supplied to the gate of the NMOS transistor 14 via level shifter (L/S) 22 and the pre-buffer 21.
The level shifter 16, level shifter 18 and pre-buffer 17, and level shifter 20, level shifter 22 and pre-buffer 21 are connected between the substrate potential VCC (>VAA) of the PMOS transistor 11 and PMOS transistor 13 and the ground. Reference numerals 23, 24, 25 and 26 denote protective diodes for the MOS transistors 11, 12, 13 and 14, respectively. The PMOS transistor 11 and PMOS transistor 13 are connected to the substrate potential VCC via parasitic diodes 27.
The logic circuit 15, level shifter 16, level shifter 18, pre-buffer 17, MOS transistor 11 and MOS transistor 12 configure an A-side driving circuit having its output terminal OUTA connected to the electrode 9 of the piezoelectric element 7. The logic circuit 19, level shifter 20, level shifter 22 pre-buffer 21, MOS transistor 13 and MOS transistor 14 configure a B-side driving circuit having its output terminal OUTB connected to the electrode 8 of the piezoelectric element 7.
In the above-described driving apparatus, when the signals shown in (a), (b), (c) and (d) of FIG. 16 are supplied to the gates of the PMOS transistor 11, the NMOS transistor 12, the PMOS transistor 13 and the NMOS transistor 14, respectively, the voltage waveforms shown in (e) and (f) of FIG. 16 occur at the output terminals OUTA and OUTB of the A-side driving circuit and the B-side driving circuit, respectively. As a result, the driving waveform shown in (g) of FIG. 16 is applied between the electrodes 8 and 9 of the piezoelectric element 7.
Specifically, in a steady state, the PMOS transistors 11 and 13 are kept in the ON state, and the NMOS transistors 12 and 14 are kept in the OFF state, thereby applying the voltage VAA to each of the electrodes 8 and 9 of the piezoelectric element 7. If the PMOS transistor 11 is turned off, and the NMOS transistor 12 is turned on at time point t1 which is slightly later than the turn-off of the transistor 11, the electrodes 9 and 8 are set at low and high levels, respectively, thereby expanding the ink chamber.
This state is maintained for a while, and the NMOS transistor 12 is turned off slightly before time period T1 elapses. At time point t2 after the time period T1 elapses, the PMOS transistor 11 is turned on to raise the potential of the electrode 9. When the PMOS transistor 13 is turned off slightly before a certain time period elapses, and the NMOS transistor 14 is turned on at time point t2′ after the certain time period elapses, the electrodes 8 and 9 are set at low and high levels, respectively, thereby contracting the ink chamber and discharging ink therefrom.
The reason why the potential of the electrode 8 is reduced when the potential of the electrode 9 is raised to a certain degree is to avoid a case where when the potential of the electrode 8 is reduced before the potential of the electrode 9 sufficiently rises, the potential of the electrode 9 is induced to the minus side by the potential reduction of the electrode 8 via the piezoelectric element 7. If the potential of the electrode 9 shifts to the minus side, current flows from the substrate of the NMOS transistor 12 at the electrode 9 side toward the electrode 9, thereby, for example, disadvantageously activating the parasitic element. Moreover, when the potential of the electrode 9 rises, an induced voltage occurs in the electrode 8. This excessively increases the level at the electrode 8, which is already at a high level. In light of this, it is necessary to set the substrate potential VCC, applied to the PMOS transistor 13, at a level higher than the excessively increased level, so that no current will flow into the substrate of the PMOS transistor 13 at the electrode 8 side.
Further, when the NMOS transistor 14 is turned off slightly before time period T2 elapses from the time point t2′, and the PMOS transistor 13 is turned on at time point t3 after the time period T2 elapses, the potential of the electrode 8 rises. Then, the potential of the electrode 8 is increased to a level identical to that of the electrode 9, whereby the piezoelectric element 7 is returned to its original state.
Then, the potential of the electrode 8 is raised, thereby inducing a voltage in the electrode 9. As a result, the level of the electrode 9, which is already at a high level, is excessively increased. In order to prevent a current from flowing into the substrate of the PMOS transistor 11 at the electrode 9 side, it is necessary to set the substrate potential VCC applied to the PMOS transistor 11 at a level higher than the excessively increased level.
As described above, in the driving apparatus using the MOS transistors, its breakdown voltage is determined from a voltage to which the one of the electrodes of the piezoelectric element, which is already at a high level, is excessively increased when the potential of the other electrode is raised. In the prior art, this increased voltage is too high, and therefore it is necessary to set, at a high level obtained by adding the increased voltage to the driving voltage VAA, the potential VCC that is to be applied to the PMOS substrate when the substrate is increased to a level higher than the driving voltage VAA. On the other hand, if the upper limit is given to the substrate potential VCC, the driving voltage VAA must be set at a low level.
In light of the above, there is a need for a method and apparatus for a capacitive element, which can suppress the peak value of the induced voltage that occurs in an electrode when charging and discharging the capacitive element, and can set a driving voltage for the capacitive element at a higher level.